This invention relates to methods for ensuring functional equivalence between implementations of a user's logic design in a programmed field-programmable gate array (“FPGA”) and a structured application-specific integrated circuit (“ASIC”).
References such as Chua et al. U.S. patent application publication 2006/0001444, Yuan et al. U.S. patent application Ser. No. 10/916,305, filed Aug. 11, 2004, Schleicher et al. U.S. patent application Ser. No. 11/050,607, filed Feb. 3, 2005, Yuan et al. U.S. patent application publication 2006/0230376, Pedersen et al. U.S. patent application Ser. No. 11/072,560, filed Mar. 3, 2005, Lim et al. U.S. patent application publication 2006/0267661, Schleicher et al. U.S. patent application publication 2006/0225008, and Tan et al. U.S. patent application publication 2006/0271899 discuss techniques for implementing a user's logic design in either a programmed FPGA or a structured ASIC. One typical objective of these techniques is for these two types of implementations to be functionally equivalent to one another. An important part of these techniques is the use of libraries of structured ASIC implementations of programmed FPGA functions that have been worked out in advance. For example, this greatly speeds up and improves the reliability of the process of providing a structured ASIC that is functionally equivalent to an FPGA programmed to perform a user's logic design. Because of the importance of these libraries, it is correspondingly important to ensure that the information contained in them will serve the intended purpose of functional equivalence.